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rev. 0.9 6/09 copyright ? 2009 by silicon laboratories an230 an230 si4700/01/02/03 p rogramming g uide 1. introduction 1.1. scope this document applies to si4700/01/02/03 firmware re vision 15 and greater and example code version 2 and greater. refer to www.mys ilabs.com for example code. 1.2. purpose the purpose of this programming guide is to describe the following: ? device initialization sequence and busmode selection ? 2-wire and 3-wire busmodes ? step-by-step procedures for ?? setting default configuration ?? channel selection ?? seek up/seek down ?? rds/rbds this document references the si4700/01 and SI4702/03 data sheets. 1.3. terminology senb or sen ?serial enable pin, active low, used only for 3-wire operation sdio?serial data in/data out pin. sclk?serial clock pin. rstb or rst ?reset pin, active low device?refers to the si4700/01/02/03
an230 2 rev. 0.9
an230 rev. 0.9 3 t able of c ontents 1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.1. scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.2. purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.3. terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2. hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1. power, initialization sequence, and busmode selection . . . . . . . . . . . . . . . . . . . . . .4 2.2. 3-wire control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.3. 2-wire control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3. software configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.1. registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2. hardware control register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3. general configuration control regi sters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4. regional confi guration control register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5. end user adjustable cont rol registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.6. seek control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7. tune control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.8. rds/rbds (si4701/03 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4. programming with commands (SI4702/03 rev c or la ter device only) . . . . . . . . . . . 26 4.1. programming in command in 2-wi re control interface mode . . . . . . . . . . . . . . . . . . 27 4.2. programming in command in 3-write control inte rface mode . . . . . . . . . . . . . . . . . 28 5. command and properties (SI4702/ 03 rev c and later device only) . . . . . . . . . . . . . . 30 5.1. SI4702/03 commands (SI4702/03 rev c or later device only) . . . . . . . . . . . . . . . 31 5.2. SI4702/03 properties (SI4702/03 rev c or later device only) . . . . . . . . . . . . . . . . 33 appendix?seek adjustability and settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
an230 4 rev. 0.9 2. hardware description 2.1. power, initialization sequence, and busmode selection figure 1. initialization sequence va,vd supply rclk pin enable bit 1234 5 rst pin vio supply
an230 rev. 0.9 5 2.1.1. hardware initialization the fm tuner device is capable of communicating using eit her a 3-wire or 2-wire interface. the selection of this interface is made during the reset sequence. figure 1 demonstrates the sequencing of hardware events relative to reset. figure 2 combines this information with the setting of the enable and disable bits to better describe the possible combinations. t he following steps should be used to initia lize the device properly. 1. supply v a and v d . 2. supply v io while keeping the rst pin low. note that power supplies may be sequenced in any order (steps 1 and 2 may be reversed). 3. configure the proper pins for bus mode selection. see figure 3, ?powerup, powerdown, and reset flowchart,? on page 7. 4. set the rst pin high. the device registers may now be read and written. 5. provide rclk. if using the internal oscillator option, set the xoscen bit. provide a sufficie nt delay before setting the enable bit to ensure that the oscillator has stabilized. the delay will vary depending on the external oscillator circuit and the esr of the cr ystal, and it should incl ude margin to allow for device tolerances. the recommended minimum delay is no less than 500 ms. a similar delay may be nece ssary for some external oscillator circuits. determine the necessary stabilization time for th e clock source in the system. to experimentally meas ure the minimum oscillator stabilization time, adjust the delay time between setting the xoscen and enable bits. after powerup, use the se t property command described in "5.1.SI4702/03 commands (SI4702/03 rev c or later device only)" on page 31 to read property address 0x0700. if the delay exceeds the minimum oscillator stabiliz ation time, the property value will re ad 0x1980 20%. if the property value is above this range, the delay time is too short. the selected delay time should include margin to allow for device tolerances. 6. si4703-c19 errata solution 2: set rdsd = 0x0000. note that this is a writable register. 7. set the enable bit high and the di sable bit low to po werup the device. unpredictable behavior could result if a non-zero value is present in the rdsd regist er of the si4703-c19 when it is enabled. note that no other device will experience this behavior. there are th ree solutions available to ensure a zero value in the rdsd register when the si4703-c19 is enabled and only one solution need be selected. a. solution 1?generate a hard reset before enablin g the tuner to clear the rdsd register. this is described in steps 2, 3, and 4 above and in step 1, to power up the device (after power down), of 2.1.2. "hardware powerdown? below. this must be done every time the tuner is enabled. b. solution 2?write a zero value to the rdsd register be fore enabling the tuner. this is described in step 6 above and must be done every time the tuner is enabled. c. solution 3?disable rds by setting rds = 0 before disabling the tuner. this is described in step 1, to power down the device, of 2.1.2. "hardware powerdown? below and must be done every time the tuner is disabled. when the device is disabled, the rdsd register is automatically set to zero in preparation for the next time the device is enabled. 2.1.2. hardware powerdown a powerdown mode is available to reduce power consumption when the part is idle. setting both the enable bit high and the disable bit high starts t he powerdown sequ ence. this disables analog and digital circuitry while maintaining register configuration and keeping the bus acti ve. note that the device automatically sets the enable bit low after the internal powerdown sequence completes. setting the enable bit low directly will cause the device to partially powerdown and should be avoided. see figu re 2. setting the enable bit high and the disable bit low will bring the device out of powerdown mo de and resume normal o peration. refer to figure 1 for more information. to power down the device: 1. si4703-c19 errata option 3: set rds = 0.
an230 6 rev. 0.9 2. set the enable bit high and the disable bit high to place the device in powerd own mode. note that all register states are maintained so long as v io is supplied and the rst pin is high. 3. remove v a and v d supplies as needed. to power up the device (after power down): 1. si4703-c19 errata option 1: perform a hard reset of t he tuner by following steps 2, 3, and 4 of 2.1.1 hardware initialization. 2. note that v io is still supplied in this scenario. if v io is not supplied, refer to devi ce initialization procedure above. 3. supply v a and v d . 4. set the enable bit high and the di sable bit low to po werup the device. setting the rst pin low will disable analog and digital circuitry, reset the registers to th eir default settings, and disable the bus. setting the rst pin high will bring the device out of reset, pl ace the device in powerdown mode, and latch which bus mode will be used to communicate wit h the device. ther e are two methods for selecting the bus mode. method one uses the sen and sdio pins while method two uses gpio1 and gpio3 (see figure 3). please refer to the data sheet for more information regar ding bus selection and timing requirements of the rst signal. more details on the register access during powerup and powerdown can be found in section "3.2.1.enable (02h.0)/disable (02h.6)?powerup control" on page 11. figure 2. powerup, powerdown, and reset state diagram low power, bus accessible normal operation undesirable, do not use low power, bus inactive powerdown read: enable = 0 disable = 0 inactive registers reset to default values bus inactive powerup read: enable = 1 disable = 0 partial powerdown read: enable = 0 disable = x rst = vio write : enable = 1 disable = 0 write : enable = 0 disable = x write : enable = 1 disable = 0 write : enable = 1 disable = 1 rst = gnd va optional vd optional vio optional rclk optional vio must be supplied prior to the rising edge of reset va optional vd optional vio required rclk optional va, vd, and rclk must be supplied prior to writing enable = 1 va required vd required vio required rclk required si4703-c19 errata: ensure rdsd register is zero before enabling. va optional vd optional vio required rclk optional device status power supply status
an230 rev. 0.9 7 figure 3. powerup, powerdown, and reset flowchart inactive gpio3 = vio? gpio1 = vio? yes control interface = 2-wire mode yes control interface = 3-wire mode no sdio = gnd? senb = gnd? yes yes no no powerdown control interface activated rst = vio? no yes bus mode select method 2 bus mode select method 1 invalid option no note: see data sheet for further details.
an230 8 rev. 0.9 2.2. 3-wire control interface for three-wire operation, a transfer begins when the sen pin is set low on a rising sclk edge. the control word is latched internally on rising sclk edges and is nine bits in length, comprised of a four bit chip address a7:a4 = 0110b, a read/write bit (read = 1 and write = 0), and a four bit register address, a3:a0. the ordering of the control word is a7:a5, r/w , a4:a0, as shown in figure 4. for write operations, the serial control word is followed by a 16-bit data word and is latched internally on rising sclk edges. the device does not latch the regist er write until the falling sclk with sen high. refer to ?3-wire control interface characteristics? and ?3-wire control interface write timing parameters? of the device data sheet for more information. figure 4. 3-wire control interface write timing diagram for read operations, a bus turn-around of half a cycle is followed by a 16-bit data word shifted out on rising sclk edges. the transfer ends on the rising sclk edge after sen is set high. note that 26 sclk cycles are required for a transfer; however, sclk may run continuously. refer to ?3-wire control inte rface characteristics? and ?3-wire control interface read timing parameters? of the device data sheet for more information. figure 5. 3-wire control interface read timing diagram a3 a2 a1 a0 d15 d14-d1 d0 a4 w a5 a6 a7 address + w = 01100xxxx data out sclk sdio sen 26 th clock required to latch the data. a3 a2 a1 a0 d15 d14-d1 d0 a4 r a5 a6 a7 address + r = 01110xxxx data in sclk sdio sen ? cycle bus turnaround 26 th clock required to latch the data.
an230 rev. 0.9 9 2.3. 2-wire control interface for two-wire operation, a transfer begins with the start c ondition. a start condition is defined as a high to low transition on the sdio pin while sclk is high. transitions for data bits must occur while the sclk pin is low. the byte following the start is the control word. the control wo rd is latched internally on rising sclk edges and is eight bits in length, comprised of a seven bit device ad dress equal to 0010000b and a read/write bit (read = 1 and write = 0). the ordering of the control word is a6:a0, r/w as shown below. the device remains in the read or write state until the stop condition is received. for write operations, the control word and device ackno wledge is followed by an eight bit data word latched internally on rising edges of sclk. the device always acknowledges the data by setting sdio low on the next falling sclk edge. any number of data bytes may be wr itten by repeating the writ e process without sending a stop condition. device register addresses are incremented by an internal address counter, starting with the upper byte of register 02h, followed by the lower byte of regist er 02h, and wrapping back to 00h at the end of the register file. the transfer is consid ered finished upon receipt of a stop condition. figure 6. 2-wire control interface write timing diagram for read operations, the control word and device acknowle dge is followed by an eight bit data word shifted out on falling sclk edges. any number of dat a bytes can be read by sending a low ack to the device. device register addresses are incremented by an internal address counter, starting at the upper byte of register 0ah, followed by the lower byte of register 0ah, and wrap ping back to 00h at the end of the regi ster file. the transfer ends with the stop conditions regardless of the state of the acknowledge. refer to ?2-wire control interface characteristics? and ?2-wire contro l interface read and write timing parameters? of the device data sheet. figure 7. 2-wire control interface read timing diagram stop a1 a0 w ack d7-d0 d7-d0 a2 a3 a4 a5 a6 address + w = 00100000 data sclk sdio ack start ack data ack ack ack stop a1 a0 ack d7-d0 d7-d0 a2 a3 a4 a5 a6 address + r = 00100001 data sclk sdio ack start ack data ack ack ack r
an230 10 rev. 0.9 3. software configuration 3.1. registers the control and status of the device is obtained thro ugh bitfields within 16 registers of 16 bits each. the functionality of the bits can be separated into two main categories: control and status. the control bits can be further subdivided into categories of when or how they ar e used (table 1). while the status bits can be classified as static, static after power up, or dynamic after power up (table 2). table 1. register use bit(s) hardware control general config regional config end user adjustable seek tune disable x enable x xoscen x ahizen x gpio1 x gpio2 x gpio3 x rdsien x stcien x blndadj x dsmute x smuter x smutea x volext x seekth x sksnr x skcnt x rdsprf x rdsm x rds x de x band x space x dmute x mono x volume x seekup x skmode x seek x tune x chan x
an230 rev. 0.9 11 3.2. hardware control registers the following set of registers alter the hardware in some way. these registers are typically the first group to be programmed. 3.2.1. enable (02h.0)/disable (02h.6)?powerup control the enable/disable bits are analogous to the on/off butto ns of the device . enable=1 turns the device on while disable=1 turns the device off (powerdown mode). when wr iting the register to place the device into powerdown mode, enable should re main set to 1 while setting disable to 1. the device clears the enable and disable bits, indicating the powerdown mode has been entered. table 3 shows the sequence of commands required to powerup the device. note that address 07h may be written during powerup configuration. table 2. status bit classification bit(s) static static after power up dynamic after power up pn x mfgid x rev x dev x firmware x st x rssi x readchan x stc x sf/bl x afcrl x rdsr x rdss x blera x blerb x blerc x blerd x rdsa x rdsb x rdsc x rdsd x
an230 12 rev. 0.9 figure 8. powerup timing table 3. powerup configuration sequence write address 07h (required for crystal oscillator operation). ? set the xoscen bit to power up the crystal. example: write data 8100h. wait for crystal to power up (required for crystal oscillator operation). ? provide a sufficient delay (minimum 500 ms) for the oscillator to stabilize. see 2.1.1. "hardwar e initialization? step 5. write address 02h (required). ? set the dmute bit to disable mute. optionally mute can be disabled later when audio is needed. ? set the enable bit high to set the powerup state. ? set the disable bit low to set the powerup state. example: write data 4001h. wait for device powerup (required). ? refer to the powerup time spec ification in table 7 "fm charac teristics" of the data sheet. read addresses 00h?01h (optional). ? the bits pn[3:0] = 1 indicate the part family: si4700/01/02/03. ? the bits mfgid[11:0] = 242h indicate s ilicon laboratories as the manufacturer. ? the bits rev[5:0] = 1 indicate silicon revision a. 2 indicates revision b. 3 indicates revision c. ? the bit(s) dev indicate the identity of the device. firmwa re 16 changed the size of the dev register from 1 bit to 4 bits and reduced firmware to 6 bits. prior to firmware 16, dev = 0 indicate the si4700 and dev = 1 indicate the si4701 after powerup. for firmware 16 and later: dev = 0000 after powerup = si4700. dev = 0001 after powerup = SI4702. dev = 1000 after powerup = si4701. dev = 1001 after powerup = si4703. ? the firmware bits indicate the firmware revision after powerup. read addresses 02h-0fh (optional) ? storing the values of each of the 16 registers locally is recommended to simplify manipulation of register bits and to reduce the number of reads/writes to the i/o bus. these are referred to as the shadow registers and can be stored in a 16 word array, shadow_reg[] . example: to write bit 15 of register 07 h after power up, write 07h as shadow_reg[0x07] ^ 0x8000 write remaining hardware configuration registers (required). write the general configuration registers (required). write the regional configuration registers (required). these registers can be programmed in any order. wr02 rd01 enable = 1 disable = 0 dev = ? optional required see powerup time in data sheet rd02-0f
an230 rev. 0.9 13 table 4 shows the sequence of commands required to power down the device. as of revision b, the tuner can optionally be programmed to place the audio output pins in to a high impedance state. if this is desired, set the ahizen bit in register 07h prior to setting the disable bit. see "3.2.3.ahi zen (07h.14)?audio high-z enable" on page 13 for more information. to reduce powerdown m ode current, gpio1/2/3 can be programmed to output a digital low (gnd). if this is desired, se t the fields gpio1-3[ 1:0] in register 04h to 10b prior to setting the disable bit. see sections 3.2.4 through 3.2.6 on page 14 and page 15 for more information. figure 9. powerdown timing 3.2.2. xoscen (07h.15)?crystal oscillator enable setting xoscen enables the in ternal oscillator. the intern al oscillator requires an ex ternal 32.768 khz crystal as shown in the data sheet schematic. if using this feature, the xoscen bit should be set at least 500 ms prior to setting the enable bit and should be clea red only after setting the disable bi t. unlike most bits, this feature will function regardless of the state of enable/disable. see 2.1.1. "hardw are initialization? step 5 for timing details. when writing to this register the state of all other bits should be maintained. this can be accomplished by first reading the register to determine the stat e of the other bits. alternatively, it is safe to assume th at the value of bits 13:0 are 0x0100 prior to power up an d are 0x3c04 after. this bit forces gp io3 to become part of the oscillator circuit and it may not be used for anything else (i.e., stereo indicator). because of this, bus mode selection method 1 must be used. 3.2.3. ahizen (07h.14)?audio high-z enable setting ahizen maintains a dc bias of 0.5 x v io on the lout and rout pins. this prevents the device diodes from clamping to v io or gnd in response to the out put swing of other devices connect ed to these pins. with this bit set, multiple audio output devices can share a single input into an amplifier without the need for a multiplexer. unlike most bits, this feature only functions wh ile the device is in power down mode and v io is supplied. when writing to this register the state of all other bits should be maintained. this can be accomplished by first reading the register to determine the state of the other bits. alternatively, it is safe to assume that the value of bits 13:0 are 0x0100 prior to power up and are 0x3c04 after. table 4. powerdown sequence write address 07h (optional for lout and rout hi-z). ? set ahizen. all other bits in this register should be main tained at the value last read (i.e., 0x3c04 or 0xbc04). example: write data 7c04h. write address 04h (optional for gpio1/2/3 low). ? set gpio1/2/3 to digital low to reduce current consumption. all other bits in this regi ster should be maintained at the value last read. example : write data 002ah. write address 02h (required). ? clear the dmute bit to enable mute. ? set the enable bit high and disable bi t high to set the powerdown state. ? after the disable bit is set high, the device performs an internal powerdown sequence and then sets the enable and disable bits low. settin g the enable bit directly to 0 will cause the device to partially powerdown. example: write data 0041h. wr02 1.5 ms max enable = 1 disable = 1 rd02 enable = 0 disable = 0 optional required
an230 14 rev. 0.9 3.2.4. gpio1 (04h.1:0)?general purpose i/o 1 gpio1 can be programmed to 3 different states as show n in table 5. this pin can be used to control an led, another device in the system, or left unused. 3.2.5. gpio2 (04h.3:2)/rdsien (04h.15)/stcien (04h.14)?general purpose i/o 2, interrupts gpio2 can be programmed to 4 different states as shown in table 6. when programmed as an interrupt, the si470x device will generate interrupts based on the settings of rdsien a nd stcien. if rdsien is set a 5 ms interrupt pulse will be generated when rds data is available. if stcien is set a 5 ms interrupt pulse will be generated upon completion of a seek or tune command. if both interrupts are enabled, the first interrupt after a seek or tune will be the stc interrupt. su bsequent interrupts will be rds inte rrupts. this pin can also be used as a general purpose output or left unused. rd s is only available on the si4701 and si4703. table 5. gpio1 states 00 high impedance (default) 01 reserved 10 low output (gnd level) 11 high output (v io level) table 6. gpio2 states 00 high impedance (default) 01 stc/rds interrupt 10 low output (gnd level) 11 high output (v io level)
an230 rev. 0.9 15 3.2.6. gpio3 (04h.5:4)?general purpose i/o 3 gpio3 can be programmed to 4 diff erent states as shown in table 7. when programmed as the mono/stereo indicator, the pin will reflect the status of the st bit. when st is set, indicating the tune r is in stereo mode, the pin will output a logic high. if the tuner s witches into mono either because of poor snr or a station that is not broadcasting in stereo, this pin will output a logic low. this pin can also be used as a general pur pose output or left unused. note that if the xoscen bit is set, gpio3 is used for the crystal oscillator and this field is ignored. 3.3. general configur ation control registers the majority of the registers are set once at initialization and then left alone. these are provided to give the designer options and trade offs so the devic e can be tailored to a specific design. 3.3.1. blndadj (04h.6:7)?stereo/mono blend level adjustment as the signal strength of a station diminishes, stereo noise can become overpowering. switching to mono under these conditions removes the noise and allows even very weak stations to be heard clearly. to improve the listening experience, the device adjusts the amount of st ereo separation based on the strength of the received rf signal. the point at which the device begins to blend ster eo and mono signals can be selected from one of the 4 settings in table 8. figure 10 demonstrat es the amount of stereo separation at a given rf level for each of the 4 settings. where each of the lines in the graph meet 0 db is the same point at which the stereo indicator bit, st, toggles. table 7. gpio3 states 00 high impedance (default) 01 mono/stereo indicator 10 low output (gnd level) 11 high output (v io level) table 8. blndadj states 00 31?49 rssi dbv (default) 01 37?55 rssi dbv (+6 db) 10 19?37 rssi dbv (?12 db) 11 25?43 rssi dbv (?6 db)
an230 16 rev. 0.9 figure 10. stereo separation 3.3.2. softmute dsmute (02h.15)\smuter (06h.15: 14)\smutea (06h.13:12)?di sable softmute\softmute attack/recover rate\softmute attenuation level to improve the listening experience when tuned to a no n-existent station or one with poor snr, the device provides a softmute feature which automatically reduces the volume significantly when the tuner detects that it isn't on a valid station. this feature can be disabled entirely by setting the dsmute bit. additionally, this feature can be adjusted for how much it attenuates the volume (smutea) as well as how quickly the attenuation is applied and removed (smuter). the available settings for smutea and smuter are shown in the tables 9 and 10 below. table 9. smutea 00 16 db 01 14 db 10 12 db 11 10 db table 10. smuter 00 fastest (default) 01 fast 10 slow 11 slowest p 22.5 khz, r=0 / l=1 -5.0 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 0 10203040506070 rssi stereo separation (db) blndadj = 00 blndadj = 01 blndadj = 10 blndadj = 11
an230 rev. 0.9 17 3.3.3. volext (06h.8)?extended volume range by default, the volume bits have a range of full scale (f s) down to fs-28 db. settin g the volext bit shifts the range by 30 db to be fs-30 db down to fs -58 db. this feature is only availabl e in firmware 16 and later. this bit has been categorized as a general configuration bit rather than user adjustment because usually one of the two ranges is sufficient for volu me adjustment. however, the usage of this bit is design dependent and depends greatly on what the lout and rout signals are being fed into. it can be used in conjunction with the volume bits to adjust the input voltage into an audio amplifier. 3.3.4. seekth (05h.15: 8)?seek rssi threshold seekth is the logarithmic received sign al strength indicator (rssi) threshol d for the seek op eration. rssi is measured as the integrated power after the channel f ilter for a given channel. channels with rssi below the seekth value will not be validated. setting the seek threshol d too high may result in mi ssed valid ch annels; too low may result in false detections. seekth is one of multiple parameters that can be used to validate channels. for more info rmation and example settings, see "appendix?seek adjustability and settings" on page 35. 3.3.5. sksnr (06h.7:4)?seek snr threshold sksnr, the signal to noise ratio thre shold for the seek operation, compar es a tuned channel's snr to an snr threshold to qualify the channel as valid. sksnr is one of multiple parameters that can be used to validate channels. for more information and example settings, see "appendix?seek adjustability and settings" on page 35. 3.3.6. skcnt (06h.3:0)?seek impulse detection threshold fm impulse noise occurs in all fm detectors when the snr of a received station becomes very low and the received noise causes the fm detector to make instantan eous phase jumps, resulting in audible ?clicks.? skcnt sets the threshold for the number of fm impulses allowed on a tuned channel within a defined period. skcnt is one of multiple parameters that can be used to validate channels. for more information and example settings, see "appendix?seek adjustability an d settings" on page 35. table 11. volext settings volext volume[3:0] fw16 (dbfs) volext volume[3:0] fw16 (dbfs) 1 0 mute 0 0 mute 1 1 ?58 0 1 ?28 1 2 ?56 0 2 ?26 1 3 ?54 0 3 ?24 1 4 ?52 0 4 ?22 1 5 ?50 0 5 ?20 1 6 ?48 0 6 ?18 1 7 ?46 0 7 ?16 1 8 ?44 0 8 ?14 1 9 ?42 0 9 ?12 1 10 ?40 0 10 ?10 1 11 ?38 0 11 ?8 1 12 ?36 0 12 ?6 1 13 ?34 0 13 ?4 1 14 ?32 0 14 ?2 1 15 ?30 0 15 0
an230 18 rev. 0.9 3.4. regional configur ation control registers while fm transmission is essentially the same around th e world, there are a few differences between countries. this group of registers allows for customization to a given region. 3.4.1. band (05h.7:6 )?fm band select this register sets the range of tunable frequencies. t he device supports 3 different ranges as shown in table 12. the low limit of the range co rresponds to what a chan of 0 represents. de pending on the seekup setting, the high limit of the range is where the seek algorithm stops or wraps back around to the low limit. 3.4.2. space (05h.5:4)?fm channel spacing the space field defines the frequency st eps that the least significant bit of the chan field represents. the device supports 3 different settings as shown in table 13. th is setting in conjunction with the band setting determines what frequency a given number in the chan regist er represents. see the description for chan for more information. the 50 khz should only be used in those countries where transmission at 50 khz spacing is allowed. for all other countr ies, the afc will automatically correct for statio ns that are transmitting slightly off carrier. selecting the proper spacing for the country the system will be used in will result in the best overall performance. 3.4.3. de (04h.11)?fm de-emphasis to reduce the amount of high frequency noise in an fm sy stem, the transmitting station boosts (pre-emphasis) the high frequency conten t expecting that the receivi ng radio will reduce (de-emphasis) the high frequency content by the same amount. the amount is specified as the time co nstant of a simple rc filter. two options are available: 75 s (0), used in the usa; and 50 s (1) used in europe, australia, and japan. 3.4.4. rds (04h.12)?rds enable (si4701/si4703 only) this bit enables/disables the rds func tion of the device. when set high, rds is enabled and when set low, rds is disabled. table 12. band ranges 00 87.5?108 mhz (us / europe, default) 01 76?108 mhz (japan wide band) 10 76?90 mhz (japan) 11 reserved (do not use) table 13. space settings 00 200 khz (us / australia, default) 01 100 khz (europe / japan) 10 50 khz 11 reserved (do not use)
an230 rev. 0.9 19 3.5. end user adjust able control registers several register fields could be tied dire ctly to an end user inte rface. most designs will ha ve an end user interface that gives access to some if not all of these features, but whether these features ar e implemented via the si470x device or some other hardware in the design is system specific. 3.5.1. dmute (02h.14)?disable mute setting this bit high disables the mute feature. the audio output of the device can be muted in two ways; either by setting this bit low or by programming the volume bits to 0. 3.5.2. mono (02h.13)?force mono many end users find it desirable to force mono on stat ions with excessive stereo noise. while the device tries to avoid this situation with the stereo/mono blend feature, this bit provides th e option to system designer. setting mono = 1 disables the stereo/mono blend feature and fo rces mono decoding of the fm baseband information regardless of signal snr. 3.5.3. volume (05h.3:0)?volume volume is self explanatory. it adjusts the signal streng th of the lout and rout pins. see the description of volext for the various settings relative to full scale output. 3.6. seek control registers one of the most powerful features of the device is the ability to au tomatically locate cha nnels with valid content. several registers control how seek behaves, however, th is section is dedicated to those registers that could possibly change upon the exec ution of any seek operation. 3.6.1. seekup (02h .9)?seek direction the device has the ability to seek for st ations in either direction. setting th is bit to 1 will cause the device to seek from the current channel up to the next available cha nnel. setting this bit to 0 will c ause the device to seek down to the next available channel. 3.6.2. skmode (02h.10)?seek band limit behavior mode the device has the ability to stop seeking when a band limit (see band) is reached or to wrap around to the other end of the band. setting this bit caus es the former behavior, i.e. if seeking up and 108 mhz is reached, the device will stop seeking and set the sf/bl bit. clearing this bit will cause the devi ce to instead wrap back to 76 or 87.5 mhz depending on the setting of band. this bit qualif ies as one that may be changed at seek time because of the various features the designer may want to provid e to the end user. for example, a feature that scans the entire band for all valid stations is most likely to begin at chan = 00 and go to the end of the band. for that feature, skmode = 1 is the best choice. however, to provide a feature that seeks up or down from the currently tuned station, skmode = 0 is likely the better choice. 3.6.3. seek (02h.8)?seek this bit indicates that the device should begin a seek operation using the currently programmed seek settings (skmode, seekup, seekth, sksnr, skcnt). the operation can be aborted by clearing th is bit, but this may leave the device on an invalid channel. during normal operat ion, the designer will leave this bit set until the device sets the stc bit. once the stc bit is set, the designer should then clear the seek bit. status of the seek operation can be obtained by polling the rea dchan register which is updated by the device as the seek progresses through the band. the following flow chart shows a typical seek algorithm. normally when sf/bl is set, the curr ent channel is invalid. ho wever, there are two exceptions. the first occurs when skmode = 0 and there is only one valid channel on the entire band. if the seek is started from that one valid channel, it will wrap the entire band and end on th e valid channel it started from. since the limit of the seek has been reached, the sf/bl bit will be set. the second exception occurs when skmode = 1 and there is a valid channel exactly at t he band limit. because the seek has hit the band limit, the bit will be se t. to check for a valid station at the band limits, tune to the station just above the lower limit. set the skmode = 0, seekup = 0, and seek = 1. if there is a valid station at the limits, it will be detected. table 14 shows the sequence of commands required for seek and assumes that the powerup configuration, detailed in section 2.1. "power, initialization sequence, and busmode selection?, has completed. this table is intended to be used in conjunction with the seek flowchart in figure 12.
an230 20 rev. 0.9 figure 11. seek timing table 14. seek up/seek down sequence write address 02h (required). ? set the skmode high to stop seek at the band limits and low to wrap at the band limits. ? set the seekup bit high to seek up and low to seek down. ? set the seek bit high to begin the seek operation. ? keep all other bits at the previously configured setting. th is is most easily done by maintaining an array of the settings. this array is referred to throughout this document and in the example code as si470x_shadow. example: skmode = 1: si470x_shadow[2] |= 0x0400 seekup = 0: si470x_shadow[2] &= ~0x0200 seek = 1: si470x_shadow[2] |= 0x0100 si470x_reg_write(2) wait for gpio2 = 0 (required for interrupt method). ? this indicates that a seek/tune operation has completed. read address 0ah (required). ? the stc bit being set indicates tuning has completed. ? the sf/bl bit being set indicates the seek operation searched the band without finding a channel meeting the seek criteria (seekth, sksnr, skcnt). ? the st bit being set indicates stereo operation. ? the bits rss[7:0] indicate rssi level for the current channel. read address 0bh (optional). ? the bits readchan[9:0] indicate the current channel. this can be read prior to stc = 1 if a seek progress indicator is desired. write address 02h (required). ? set the seek bit low to end the tuning operation and to set the stc bit low. example: write data to 4001h. read address 0ah (optional). ? the stc bit being cleared indi cates that the tune or seek bi ts may be set again to st art another tune or seek operation. do not set the tune or seek bi ts until the si470x clears the stc bit. wr02 rd0a see datasheet for timing seek = 1 stc = 1 rd0b wr02 seek = 0 stc = 0 1.5 ms max wr02 seek = 1 5 ms min gpio2 first seek second seek optional required rd0a
an230 rev. 0.9 21 figure 12. seek flowchart scan entire band? set chan=00 set skmode=1 seek up? set seekup=1 set skmode=0 set seekup=0 seek requested set seek=1 read register 0x0a, 0x0b stc set? no update display with readchan information no no yes scan entire band? yes stc cleared? no yes yes seek complete current station valid no stored sf/bl set? set seek=0 yes seek complete current station not valid no yes store readchan as a valid station store the status of sf/bl bit wait 60ms if using the stc interrupt on gpio2, these steps can be removed. this is recommended when using the internal crystal oscillator. (please see errata) ?seek/tune time? see datasheet for official value.
an230 22 rev. 0.9 3.7. tune control registers 3.7.1. tune (03h.15)\chan (03h.9:0)?tune\channel select setting the tune bit initiates the tuning process causing the device to switch to the frequency indicated by chan. the actual frequency that chan refers to depends on the band and space settings and can be determined as follows: where: ?? f is desired frequency in mhz ?? s is space between channels in mhz (0.050, 0.100, or 0.200 mhz) ?? c is integer channel setting ?? l is minimum band limit in mhz as set by band (76 or 87.5 mhz) f = s x c + l as an example, if band = 00, space = 01, and chan = 148, the frequency is 0.1 x 148 + 87.5 = 102.3 mhz when the device completes the tuning process, the stc bit is set. the maximum time that the process takes is specified in the data sheet as "seek/tune time". if gpio 2 is configured as an stc interrupt, the gpio2 pin will pulse low for a minimum of 5ms. to clear the stc bit, clear t he tune bit. it is important to verify that the stc bit is cleared before performing another seek or tune. table 15 shows the sequence of commands required fo r channel selection and assumes that the powerup configuration, de tailed in section 2.1. "power, initialization sequence, and busmode selection?, has completed. table 15. channel selection sequence write address 03h (required). ? set the tune bit high to begin a tuning operation. ? set chan[9:0] bits to select the desired channel. example: to tune to 103.5 mhz in the united states, with band[1:0] = 00 and space[1:0] = 00 as described in the powerup sequence, set chan[9:0] = 80d = 50h such that frequency = 103.5 mhz = 0.200 mhz x 80 + 87.5 mhz). write data 8050h. wait for gpio2 = 0 (required for interrupt method). ? this indicates that a seek/tune operation has completed. read address 0ah (optional for interrupt method, required for polling method). ? the stc bit being set indicates tuning has completed. ? the st bit being set indicates stereo operation. ? the bits rssi[7:0] indicate rssi level for the current channel. read address 0bh (optional). ? the bits readchan[9:0] indicate the current channel. write address 03h (required). ? set the tune bit low to end the tuning operation and to set the stc bit low. example: write data to 0050h. read address 0ah (optional). ? the stc bit being cleared indi cates that the tune or seek bi ts may be set again to st art another tune or seek operation. do not set the tune or seek bi ts until the si470x clears the stc bit.
an230 rev. 0.9 23 figure 13. channel selection timing figure 14. channel selection flowchart wr03 rd0a see datasheet for timing tune = 1 stc = 1 rd0a rd0b wr03 tune = 0 stc = 0 1.5 ms max wr03 tune = 1 5 ms min gpio2 first tune second tune optional required set chan tune requested set tune=1 read register 0x0a stc set? yes stc cleared? no tune complete set tune=0 yes if using the stc interrupt on gpio2, these steps can be removed. this is recommended when using the internal crystal oscillator. (please see errata) wait 60ms no this will never occur if the ?seek/ tune time? delay is met. ?seek/tune time? see datasheet for official value.
an230 24 rev. 0.9 3.8. rds/rbds (si4701/03 only) table 16 shows the sequence of commands required for rds and assumes that the powe rup, initialization, and regular configuration has completed. the flow chart in figure 16 should be used in conjunction with the example code found in rds.c. for more information on rds, please refer to ?an243: using rds/rbds with the si4701/03". figure 15. rds timing table 16. rds/rbds sequence write address 02h (optional). ? select the rds mode to use: standard or verbose. standard mode only returns fully corrected data while verbose mode indicates the number of errors corrected in each block. write address 04h (required for interrupt method). ? set the rdsien bit high to enable a low interrupt on gpio2 when rds data are ready. ? set the rds enable bit (rds = 1). ? set gpio2[1:0] = 01 to enable stc and rdsr interrupts on gpio2. example: to enable rds operation with rds interrupts and seek/tune interrupts enabled, write data d004h. wait for gpio2 = 0 (required for interrupt method). ? this indicates that rds data are ready. read address 0ah (optional for interrupt method, required for polling method). ? the rdsr bit being set indicates rds data are ready (si4701 only). ? if in verbose mode, the blera bits indicate how many er rors were corrected in blo ck a. if blera indicates 6 or more errors, the data in rdsa should be discarded. ? when using the polling method, it is be st not to poll continuous ly. the data will appear in intervals of ~88 ms and the rdsr indicator will be availa ble for at least 40 ms, so a polling rate of 40 ms or less should be sufficient. read address 0bh (optional). ? if in verbose mode, the blerb, blerc, and blerd bits indicate how many errors were corrected in the respective blocks. if blerb indicates 6 or more errors, all 3 blocks of data should be discarded. if blerc or blerd indicate 6 or more errors, then just the respective block may be discarded. read addresses 0ch?0fh (required). ? the bits rdsa[15:0], rdsb[15:0], rdsc[15:0], and rd sd[15:0] contain error-corrected rds group data. wr04 rd0e 87.6 ms rdsien = 1 rd0a rd0c rd0d rd0f 5 ms min gpio2 first group second group optional required rdsr rd0a 40 ms min configuration wr02 rd0b
an230 rev. 0.9 25 figure 16. rds flowchart rdsr? read registers 0a-0f and store as local shadow rds idle blera < 3 update pi code blerb < 2 update pi code with rdsa blerb < 2 group type = rdsb >> 11 group type b? optionally update pi code with rdsc if bler < 3 update pty code with rdsb[9:5] group type? update af tracking with rdsc blerc < 3 blerd < 3 update ps with rdsd 0a yes yes yes yes yes yes no no rds done no 0b blerc < 3 update rt with rdsc blerd < 3 update rt with rdsd 2a yes yes 2b blerb + blerc + blerd = 0 4a no no no yes update clock with rdsc and rdsd no no group decode group decode no only update the time if there were no errors because block b determines what c and d are used for, place a more strict error limit.
an230 26 rev. 0.9 4. programming with commands (si4 702/03 rev c or la ter device only) the SI4702/03-c device provides additional functions an d features that are not available in the SI4702/03-b16 device, while maintaining backward comp atibility to the si470 2/03-b16 register set. in addition to the register- based programming method, the SI4702/03-c devi ce may be programmed using commands, arguments, properties, and responses. commands control actions, such as set property value or get property value, and are one byte in size. arguments are specific to a given command and are used to modify the command. for example, the property_index argument is required for the get_property command . arguments are one byte in size, and each command may require up to seven arguments. responses provide the system controller status info rmation and returned after a command bits associated arguments are issued. comman ds may return up to 7 additional response bytes. a complete list of commands is available in 5. "command and properties (SI4702/03 rev c and later device only)?. the command interface uses the rdsa, rdsb, rdsc and rd sd registers. in order to send commands rds bit (register 4, bit 12) must be disabled for the dur ation of the command processing by setting rds = 0. to send a command, write registers 0ch?0fh (rdsa?rdsd) with the desired arguments and command, then poll register 0fh (rdsd) until the least signi ficant byte is 0x00. at this point th e response (if applicable) is available in registers 0ch?0fh (rdsa?rdsd). there will be a delay between the time th at rds bit is set to 0 and a command may be sent. in order to determine when the command processor is enabled, write register 0fh to 0x00ff and poll until register 0fh is 0x0000. responses provide the user information and are echoed after a command and associated arguments are issued. table 17. format for programming with commands (SI4702/03 rev c or later device only) register name register address command high low rdsa command1 0ch arg0 arg1 rdsb command2 0dh arg2 arg3 rdsc command3 0eh arg4 arg5 rdsd command4 0fh arg6 cmd register name register address response high low rdsa response1 0ch resp0 resp1 rdsb response2 0dh resp2 resp3 rdsc response3 0eh resp4 resp5 rdsd response4 0fh resp6 status
an230 rev. 0.9 27 4.1. programming in command in 2-wire contro l interface mode table 18 demonstrates the command and response procedur e implemented in the system controller to use the 2- wire bus mode. in this example the get_property command is demonstrated. in 2-wire mode, care must be taken to write regist er 02h?0bh with the original values since the rdsa?rdsd register are at the end of the 2-wire mode. to send the get_property command and arguments, the system controller sends the start condition, followed by the 8-bit control word, which consists of th e seven-bit address (00100000b) and the write bit (0b). the device acknowledges the control word by setting sd io = 0, indicated by ack = 0. the system controller then sends the reg 02h hi byte, and again the device a cknowledges by setting ack = 0. the system controller and device repeat this process for reg 02h lo, reg 03h hi?reg 0bh lo, arg0, arg1, arg2, arg3, arg4, arg5, arg6, and cmd byte. all seven arguments bytes must be sent for all commands, and unused arguments must be written 0x00. to read the status and response from the device, the system controller sends the start condition, followed by the eight-bit control word, which consists of seven bit device address and the read bit (1b). in this example, the write control word is addr+r = 00100001b = 0x21. the device acknowledges the control word by setting ack = 0. next the system controller reads the reg 0ah hi byte. th e system controller and devi ce repeat this process for the reg 0ah lo, reg 0bh hi, reg 0bh lo, resp 0, resp1, resp2, resp3, resp4, resp5, resp6, and status bytes. in this example, status byte is 0x08, indicating that the data are not ready. the response bytes are not valid and must be ignored. this process is repeated until the status byte is set to 0x00. table 18. command and response procedure?2-wire bus mode (SI4702/03 rev c or later device only) action data description reg 02h?0bh write 0x-- write with the original value. arg0 write 0x00 arg1 write 0x00 arg2 write 0x00 arg3 write 0x00 arg4 write 0x03 property_index high byte arg5 write 0x01 property_index low byte arg6 write 0x00 cmd write 0x08 get_property for blend_stereo_rssi reg 0ah?0bh read 0x-- read starts from register 0ah. resp0?6 read 0x-- response data are only valid when status is set to 0x00. status read 0x08 reply status. response data are not valid. reg 0ah?0bh read 0x-- read starts from register 0ah. resp0?6 read 0x-- response data are only valid when status is set to 0x00. status read 0x00 reply status. response data are valid. start addr + w ack reg 02h hi ack reg 02h lo ack ? ack reg 11h lo ack arg0 ack ? arg6 ack cmd ack stop start 0x20 0 0x-- 0 0x-- 0 ? 0 0x-- 0 0x00 0 ? 0x00 0 0x08 0 stop
an230 28 rev. 0.9 when the status byte returns 0x00, the system controlle r may use the response bytes from the device. however, unused response bytes return random data and must be ignored. 4.2. programming in command in 3-write control interface mode table 19 demonstrates the command and respond proced ure implemented in the system controller to use the 3- wire bus mode. in this example, get_property command is demonstrated. in 3-wire mode, register 0fh must be the last register written. to send the get_property command and arguments, the system controller sets sen = 0. next, the controller drives the 9-bit control word on sd io, consisting of the device address (a7:a5 = 101b), the write bit (0b), the device address (a4 = 0b), and register address for the command1 register (a3:a0 = 1100b). the control word is followed by a 16-bit data word, consisting of arg0 followed by arg1. the system controller then sets sen =1 and pulses sclk high and then low one final time. next, the controller sends arg2 and arg3 of the command by driving drives the 9-bit control word on sdio, consisting of the device address (a7:a5 = 101b), the writ e bit (0b), the device address (a4 = 0b), and register address for the command2 register (a3:a0 = 1101b). the control word is followed by a 16-bit data word, consisting of arg2 followed by arg3. the system controller then sets sen = 1 and pulses sclk high and then low one final time. next, the controller sends arg4 and arg5 of the command by driving drives the 9-bit control word on sdio, consisting of the device address (a7:a5 = 101b), the writ e bit (0b), the device address (a4 = 0b), and register address for the command3 register (a3:a0 = 1110b). the control word is followed by a 16-bit data word, consisting of arg4 followed by arg5. the system controller then sets sen = 1 and pulses sclk high and then low one final time. start addr + r ack reg 0ah hi ack reg 0ah lo ack reg 0bh hi ack reg 0bh lo ack resp0 ack ? resp6 ack status ack stop start 0x21 0 0x-- 0 0x-- 0 0x-- 0 0x00 0 0x-- 0 ? 0x-- 0 0x08 0 stop start addr + r ack reg 0ah hi ack reg 0ah lo ack reg 0bh hi ack reg 0bh lo ack resp0 ack ? resp6 ack status ack stop start 0x21 0 0x-- 0 0x-- 0 0x-- 0 0x00 0 0x-- 0 ? 0x-- 0 0x00 0 stop table 19. command and response procedure?3-wire bus mode (SI4702/03 rev c or later device only) action data description arg0/1 write 0x0000 arg2/3 write 0x0000 arg4/5 write 0x0301 property_index arg6/cmd write 0x0008 get_property for blend_stereo_rssi resp6/status read 0x0008 reply status. data is not ready. resp6/status read 0x0000 reply status. data is ready. sen control arg0 arg1 sen sclk 1 ? 0 10101100b 0x00 0x00 0 ? 1pulse sen control arg2 arg3 sen sclk 1 ? 0 10101101b 0x00 0x00 0 ? 1pulse
an230 rev. 0.9 29 next, the controller sends arg6 and cmd of the command by driving drives the 9-bit control word on sdio, consisting of the device address (a7:a5 = 101b), the writ e bit (0b), the device address (a4 = 0b), and register address for the command4 register (a3:a0 = 1111b). the control word is followed by a 16-bit data word, consisting of arg6 followed by cmd. the system controller then sets sen = 1 and pulses sclk high and then low one final time. to read the status and response from the device, the system controller sets sen = 0. next, the controller drives the 9-bit control word on sdio, consisting of the device addr ess (a7:a5 = 101b), the read bit (1b), the device address (a4 = 0b), and register address for t he response4 register (a3:a0 = 1111b). the control word is followed by a 16-bit data word, consisting of resp6 followed by status. the system controller then sets sen = 1 and pulses sclk high and then low one final time. in this example, the status byte is 0x08, indicating that the response data are not ready. the device is not ready to accept another command. resp6 is random until the status byte is 0x00. this process should be repeated until the status byte is set to 0x00. when the status byte is set to 0x00, the system contro ller may read the response bytes from the device in any order. if the reply included resp0 and resp1 by tes, the system controller sets sen = 0, and then the controller drives the 9-bit control word on sdio, consisting of the devic e address (a7:a5 = 101b), the read bit (1b), the device address (a4 = 0b), and regi ster address for th e response1 register (a3:a0 = 1100b). the control word is followed by a 16-bit data word, cons isting of resp0 followed by resp1. the system controller then sets sen =1 and pulses sclk high and then low one final time. sen control arg4 arg5 sen sclk 1 ? 0 10101110b 0x03 0x00 0 ? 1pulse sen control arg6 cmd sen sclk 1 ? 0 10101111b 0x00 0x08 0 ? 1pulse sen control resp7 status sen sclk 1 ? 0 10111111b 0x00 0x08 0 ? 1pulse sen control resp7 status sen sclk 1 ?? 0 10111111b 0x00 0x00 0 ? 1pulse sen control resp0 resp1 sen sclk 1 ? 0 10111101b 0x-- 0x-- 0 ? 1pulse
an230 30 rev. 0.9 5. command and properties (si4 702/03 rev c and l ater device only) table 20. SI4702/03 command summary (SI4702/03 rev c or later device only) cmd name description 0x07 set_property sets the value of a property. 0x08 get_property retrieves a property's value. 0xff verify_command this command can be used to determine that the command processor is enabled.
an230 rev. 0.9 31 5.1. SI4702/03 commands (si 4702/03 rev c or later device only) command 0x07 set property sets a property shown in section 5.2. "SI4702/03 properties (SI4702/03 rev c or later device only)?. this command may only be sent when in powerup mode. response bytes: none command bitd7d6d5d4d3d2d1d0 cmd000 0 0 1 1 1 arg0 property_value[15:8] arg1 property_value[7:0] arg2 always write to 0 arg3 always write to 0 arg4 property_index[15:8] arg5 property_index[7:0] arg6 always write to 0
an230 32 rev. 0.9 command 0x08 get property gets a property shown in section 5.2. this command may only be sent when in powerup mode. response bytes: two command response command 0xff verify_command this command can be used to determine that the command processor is enabled. send this command and poll to see that the command byte has been cleared. response bytes: none command bitd7d6d5d4d3d2d1d0 cmd000 0 1 0 0 0 arg0 always write to 0 arg1 always write to 0 arg2 always write to 0 arg3 always write to 0 arg4 property_index[15:8] arg5 property_index[7:0] arg6 always write to 0 bitd7d6d5d4d3d2d1d0 resp0 property value [15:8] resp1 property value [7:0] bitd7d6d5d4d3d2d1d0 cmd111 1 1 1 1 1 arg0 always write to 0 arg1 always write to 0 arg2 always write to 0 arg3 always write to 0 arg4 always write to 0 arg5 always write to 0 arg6 always write to 0
an230 rev. 0.9 33 5.2. SI4702/03 properties (SI4702 /03 rev c or later device only) property 0x0200. fm_detector_snr (default 0) selects the snr where the fm detector switches modes. default of 0 is backward compatible with SI4702/03-b16 fm detector. snr >12 ? differential detector 12 > snr > threshold ? impulse reject detector threshold > snr > 0 ? slew rate detector property 0x0300 blend_mono_rssi (default 31) sets the rssi level to enable full mono audio output. at rssi levels more than blend_mono_rssi, but less than blend_stereo_rssi, stereo separa tion will be reduced. if this property is used , it is re commended that the blendadj bits be set to 0. bit d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 00000000 fdsnr[7:0] bit name function d15:d8 reserved always write to 0. d7:d0 fdsnr sets threshold for fm detector. bit d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 00000000 bmr[7:0] bit name function d15:d8 reserved always write to 0. d7:d0 bmr sets threshold for full mono audio output.
an230 34 rev. 0.9 property 0x0301 blend_stereo_rssi (default 50) sets the rssi level to enable full stereo audio output. at rssi levels more th an blend_mono_rssi, but less than blend_stereo_rssi, stereo separa tion will be reduced. if this property is used , it is re commended that the blendadj bits be set to 0. property 0x0700 calcode (default n/a) read-only internal calibration result of the powe rup sequence. this re sult may be used to troubl eshoot crystal oscillator/rclk operation. see 2.1.1. "hardware initialization? step 5. property 0x0c00 snrdb (default n/a) read-only snr level (in 2 db steps) that the seek algorithm is seeing. fm_detector_snr uses this value to compare to the threshold. bit d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 00000000 bsr[7:0] bit name function d15:d8 reserved always write to 0. d7:d0 bsr sets threshold for full stereo audio output. bit d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name calcode[15:0] bit name function d15:d0 calcode internal calibration result of the powerup sequence. bit d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 00000000 s nrdb[7:0] bit name function d15:d8 reserved always write to 0. d7:d0 snrdb snr level (in 2 db steps) that the seek algorithm is compared to.
an230 rev. 0.9 35 a ppendix ?s eek a djustability and s ettings introduction an important feature of an fm radio receiver is it s ability to reliably identify valid stations during a seek operation. this feature allows end customers to seek from one valid station to the next up and down the fm band. it also allows manufacturers to create host software to automatic ally populate a list of valid stations in a given area. however, reliably identifying and separating valid stations from noise or p oor-quality stations is challenging in any environment, especially portable devi ces. the silicon laboratorie s si4700/01/02/03 fm tu ner family provides a highly reliable seek algorithm, and also adds adjustability so that manufact urers and/or end users can customize seek settings to accommodate individual tastes or changing rf environments. default seek qualifiers the most commonly used measurement of valid stations is the total received power at a given channel compared to a threshold. in the si4700/01/02/03 family, this power measurement is received signal strength indicator (rssi), measured as the integrated powe r after the channel filter for a given channel. the rssi seek threshold (seekth) is simply the power level abo ve which a valid channel is determined. setting th e seek threshold too high may result in missed valid channels; too low may resu lt in false detections. to augment the accuracy of this metr ic, the si4700/01/02/03 incorporates a second indicator of valid channels called automatic frequency control rail, or afc rail. afc rail is used to dete ct the condition wherein an adjacent channel's power is detected at the tuned frequency, potent ially detecting a false positive. if a tuned channel?s rssi is above the seek threshold, but the afc has tracked from the center of the channel by a given number of khz, the channel can reliably be determined to be an invalid station. using the rssi threshold in conjunction with afc rail offers seek per formance with a greater than 90% probability of finding only valid stations and a sub-4 second scan time for auto-populating valid stations. note: figures given represent a com petitive host micro-controller , 200 khz channel spacing, and 87.5?108 mhz band setting.
an230 36 rev. 0.9 advanced seek offerings fm environments typically generate a shaped noise profile, making it almost impossible to set a seek threshold which is both above the noise floor and within valid station levels. the noise floor can vary due to many factors including antenna impedance and matching, signal enviro nment, agc setting, and noise sources. in particular, office and lab environments have elevated noise levels acro ss the fm band due to the presence of electronic and computer equipment. an example rssi spectrum is s hown below in figure 17. note that valid stations are indicated by their frequencies. figure 17. sample rssi spectrum in figure 17, the valid stations at 93.3, 98.9, 104.9, 105.9, and 107.1 are difficult to detect since their rssi levels are below the noise level of the spectrum at some unpo pulated channels. setting the rssi seek threshold to a value of 12 would likely detect these valid stations, but could have false positi ves at many invalid channels. setting the seek threshold to 22 as shown avoids false detections but could miss these valid stations. the si4700/01/02/03 devices incorporate additional valid station qualifiers to more reliably detect lower rssi stations and screen out invalid stations. these qualifiers are optional and adjustable so that customers and end users may adjust seek as desired. the additional qualifiers run sequentially to the first two tests discussed above. the first qualifier, snr, compares a tuned channel's snr to an snr threshold. the snr thre shold is adjustable in sksnr[3:0]. example sksnr[3:0] threshold values and likely results are shown in table 21. 107.1 105.9 104.9 103.5 102.3 101.5 100.7 98.9 98.1 96.7 95.5 94.7 93.7 93.3 90.5 89.5 88.7 0 5 10 15 20 25 30 35 40 45 87.5 89.5 91.5 93.5 95.5 97.5 99.5 101.5 103.5 105.5 107.5 channel frequency rssi level db ? v rssi sweep seek threshold
an230 rev. 0.9 37 the second qualifier in si4700/01/02/03 devices measures the number of fm impulses detected at a tuned channel. fm impulse noise occurs in all fm detectors when the snr of a received station becomes very low and the received noise causes the fm detector to make instan taneous phase jumps, resulting in audible "clicks." for a noisy signal, more fm impulses are typically received, an d conversely for a higher quality signal, fewer or no fm impulses are received. the si4700/01/02/03 detects thes e fm impulses and applies a smoothing filter to minimize their impact on sound quality. fm impulses can also be used as a metric to determine the quality of the audio present on a given channel. this qualifier is optional and adjustable. the skcnt register sets a threshold for the number of fm impulses allowed on a tuned channel within a defined period. note: the period and algorithm for measuring fm impulses is propriet ary to silicon laboratories, inc. and will not be explained further. table 22 provides some example settings and approximate results. note: by increasing the stringency of sksnr and skcnt settings, st ations that have low snr or high levels of fm impulse noise may be rejected. typically, these stations do not have good audio quality and customers do not wish to listen to them; however, if customers are specifically searching for these stations, be aware that a stringent seek algorithm may disqualify them as valid stations. table 21. sample sksnr[3:0] settings sksnr[3:0] write value desired snr threshold seek result relative to default seek metrics 0x0 disabled na 0x4 good snr threshold incre ased reliability, only good stations qualified 0x7 better snr threshold increased reliabilit y, only better stations qualified table 22. sample skcnt[3:0] settings skcnt[3:0] write value desired impulse threshold seek result relative to default seek metrics + snr threshold 0x0 disabled na 0x8 allows more fm impulses increased re liability, more stringent valid station requirements 0xf allows fewer fm impulses highest relia bility, most strin gent valid station requirements
an230 38 rev. 0.9 seek algorithm sequencing the seek algorithm sequencing is sh own in the flowchart in figure 18. figure 18. seek algorithm flowchart note: both snr and fm impulse count are independent and can be run as additional qualifiers with or without the other. channel rssi > seekth afc rail set? yes sksnr enabled no invalid station yes no channel snr > sksnr threshold yes no skcnt enabled fm impulses < skcnt threshold yes yes valid station no no yes no
an230 rev. 0.9 39 seek results comparisons figure 19 compares silicon lab oratories field trials with existing and new seek parame ters. the graph illustrates that by setting the rssi seek threshold at 25, invalid ch annels are not detected; however several valid stations are missed. conversely, with the rssi threshold at 12, severa l invalid stations are identif ied. with the new optional qualifiers enabled with the rssi threshold at 12, the inva lid stations are rejected and valid stations are reliably identified. figure 19. seek results comparison 88.7 89.5 90.5 93.7 94.7 95.5 100.7 102.3 93.3 107.1 105.9 104.9 103.5 101.5 98.9 96.7 98.1 0 5 10 15 20 25 30 35 40 45 87.5 92.5 97.5 102.5 107.5 channel frequency rssi level db ? v rssi sweep seekth=12,cnt=8,snr=4 valid stations seekth=12 invalid channels seekth=12 valid stations seekth=25 invalid station rejected by snr and cnt invalid stations rejected by snr and cnt valid stations missed with seekth at 25
an230 40 rev. 0.9 seek settings recommendations table 23 summarizes the seek settings discussed above. these settings are adjustable to address customers? system design, target markets, and subjective preferences and have been found to yield good performance in most applications. table 23. summary of seek settings configuration comments seekth [7:0] sksnr[3:0] skcnt[3:0] default compatible with firmware 14 0x19 0x0 (disabled) 0x0 (disabled) recommended relative to firmware 14 0x19 (typical) 0x4?good snr 0x8?fewer fm impulses more stations reduced seekth identifies valid stations in low rssi environments 0xc (typical) 0x4?good snr 0x8?fewer fm impulses good quality stations only identifies only good quality stations 0xc 0x7?better snr 0xf?fewest fm impulses most stations seek algori thm relies solely on afc rail, snr and fm impulse; most valid stations identified; potential for slightly longer seek time 0x0 0x4?good snr 0xf?fewest fm impulses
an230 rev. 0.9 41 d ocument c hange l ist revision 0.42 to revision 0.43 ? added sections 4. "programming with commands (SI4702/03 rev c or later device only)? and 5. "command and properties (SI4702/03 rev c and later device only)?. revision 0.43 to revision 0.44 ? updated "4.1.programming in command in 2-wire control interface mode" on page 27. ? updated command register "property 0x0200. fm_detector_snr (default 0)" on page 33. revision 0.44 to revision 0.5 ? added si4703-c19 errata description: ?? updated 2.1.1 hardware initialization. ?? updated 2.1.2 hardware powerdown. ?? updated figure 2 on page 6. revision 0.5 to revision 0.6 ? added "appendix?seek ad justability and settings?. ? expanded sections 3.3.4?3.3.6 ? added description of setting gpio1/2/3 low to ta b l e 4 . ? clarified section 3.2.1 and table 3. ? removed nda. revision 0.6 to revision 0.61 ? added 0.5 to 0.6 revision list. revision 0.61 to revision 0.62 ? updated table 20, ?SI4702/03 command summary (SI4702/03 rev c or later device only),? on page 30. revision 0.62 to revision 0.7 ? updated table 21, ?sample sksnr[3:0] settings,? on page 37 and table 23, ?summary of seek settings,? on page 40. revision 0.7 to revision 0.8 ? updated blend_mono_rssi, blend_stereo_rssi property index in tables 18, 19, and section 5.2. revision 0.8 to revision 0.9 ? updated "2.1.1.hardware initialization" on page 5 step 5. ? updated register , ?property 0x0c00 snrdb (default n/a) read-only,? on page 34.
disclaimer silicon laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the silicon laboratories products. characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "typical" parameters provided can and do vary in different applications. application examples described herein are for illustrative purposes only. silicon laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. silicon laboratories shall have no liability for the consequences of use of the information supplied herein. this document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. the products must not be used within any life support system without the specific written consent of silicon laboratories. a "life support system" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. silicon laboratories products are generally not intended for military applications. silicon laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. trademark information silicon laboratories inc., silicon laboratories, silicon labs, silabs and the silicon labs logo, cmems?, efm, efm32, efr, energy micro, energy micro logo and combinations thereof, "the world?s most energy friendly microcontrollers", ember?, ezlink?, ezmac?, ezradio?, ezradiopro?, dspll?, isomodem ?, precision32?, proslic?, siphy?, usbxpress? and others are trademarks or registered trademarks of silicon laboratories inc. arm, cortex, cortex-m3 and thumb are trademarks or registered trademarks of arm holdings. keil is a registered trademark of arm limited. all other products or brand names mentioned herein are trademarks of their respective holders. http://www.silabs.com silicon laboratories inc. 400 west cesar chavez austin, tx 78701 usa smart. connected. energy-friendly products www.silabs.com/products quality www.silabs.com/quality support and community community.silabs.com

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